Sample-and-hold (S/H) circuits are used in systems when a varying analog input voltage signal needs to be sampled and processed at a later time. For instance, in one application, a S/H circuit may be used to temporarily store an analog signal until such time as an analog-to-digital converter can convert the signal level to a digital. A S/H circuit acquires an analog input voltage signal sampled at an instant and stores or “holds” the voltage sample for a time duration (i.e., specified period of time) on a hold capacitor before processing so that it may be converted to a digital value. S/H circuits have two operating states or modes—sample mode and hold mode. During a an acquisition or “sample” mode, a control signal closes a switch (e.g., a metal oxide semiconductor field-effect transistor (FET)) so that an analog input voltage signal representation is present on the hold capacitor. During a “hold” mode, a switch in the S/H circuit is opened, and the sampled signal that is stored on the hold capacitor is available as an output voltage.
Desired characteristics of a S/H circuit include short acquisition time during the sample mode and low voltage droop during hold mode. To explain further, there is a settling time after the sample command until the output reaches its value representing the input. After the hold command, an aperture time is the time after which changes of the input voltage no longer affect the output voltage signal. The sample or “acquisition” time is the time for the output voltage signal to settle within an accuracy (e.g., 0.1%) of the input voltage being acquired. In other words, the acquisition time represents the amount of time required for the hold capacitor to charge to a voltage level which accurately corresponds to the input signal. When the S/H circuit is in hold mode, the voltage droop rate (μV/μs) refers to the change in the output voltage that is being “held” over time due to leakage currents.
While short acquisition time and low voltage droop are desirable, optimizing the performance of S/H circuit necessarily involves making compromises since improving one parameter tends to degrade the other. Among other things, the acquisition time and voltage droop rate depend on the size of the hold capacitor. A larger hold capacitor decreases voltage droop, but increases acquisition time since it takes longer for the hold capacitor to charge. By contrast, a smaller hold capacitor decreases acquisition time since the hold capacitor can charge more quickly, but increases voltage droop since there is less capacitance, and therefore the effect of a given amount of leakage current is greater.
A common problem in many sample-and-hold circuits is leakage current. As used herein, the term “leakage” refers to a gradual change in stored charge on a charged hold capacitor. Leakage is caused by the unwanted transfer of charge from electronic devices that are coupled to the hold capacitor, such as a transistor or diode, either of which conducts a small amount of current even when turned off. For instance, tunneling leakage can occur through semiconductor junctions between heavily doped P-type and N-type diffusions. Sub-threshold leakage occurs when carriers can leak between a source and a drain of a Metal Oxide Semiconductor (MOS) transistor when the gate-to-source voltage (VGS) is below the threshold voltage (VTH).
During the hold mode, leakage currents can cause the output voltage sample being held on the hold capacitor to droop (i.e., discharge) or to increase, depending on the polarity of the leakage current. In other words, the voltage droop is dependent on the leakage current from the hold capacitor to other components connected thereto including a S/H switch. To reduce voltage droop during hold mode it is desirable to reduce current flow from the hold capacitor. One approach to reducing voltage droop is to simply increase the size of the hold capacitor (e.g., to much greater than 100 picofarads), but as noted above, this increases acquisition time and also increase the size and therefore the cost of this component. For example, in applications where a very long hold time (e.g., 100 milliseconds) is required, there is longer period for charge to leak from the hold capacitor and cause drooping of the output voltage sample that is being held by the hold capacitor. At the same time, it may not be feasible to increase the size of the hold capacitor if other constraints exist (e.g., constraints regarding acquisition time). In situations where simply increasing the size of the hold capacitor is not an option, more creative solutions are needed to reduce leakage currents
It is desirable to provide an improved sample-and-hold circuit with improved performance. For example, it is desirable to provide an improved sample-and-hold circuit that is designed to have a long hold time and low voltage droop during this long hold time. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.